Ibex Reference Guide

The Ibex Reference Guide provides background information. It describes the design in detail, discusses the verification approach and the resulting testbench structures, and generally helps to understand Ibex in depth.

In this section

• Pipeline Details
  • Third Pipeline Stage
  • Multi- and Single-Cycle Instructions
• Instruction Cache
  • High-level operation
  • Configuration options
  • Performance notes
  • RAM Arrangement
  • Sub Unit Description
• Instruction Fetch
  • Branch Prediction
  • Instruction-Side Memory Interface
  • Misaligned Accesses
  • Protocol
• Instruction Decode and Execute
  • Instruction Decode Block (ID)
  • Controller
  • Decoder
  • Register File
  • Execute Block
  • Arithmetic Logic Unit (ALU)
  • Multiplier/Divider Block (MULT/DIV)
  • Control and Status Register Block (CSR)
  • Load-Store Unit (LSU)
• Load-Store Unit
  • Data-Side Memory Interface
  • Bus Integrity Checking
  • Misaligned Accesses
  • Protocol
• Register File
  • Flip-Flop-Based Register File
  • FPGA Register File
  • Latch-Based Register File
• Control and Status Registers
  • Machine Status (mstatus)
  • Machine ISA Register (misa)
  • Machine Interrupt Enable Register (mie)
  • Machine Trap-Vector Base Address (mtvec)
  • Machine Exception PC (mepc)
  • Machine Cause (mcause)
  • Machine Trap Value (mtval)
  • Machine Interrupt Pending Register (mip)
  • PMP Configuration Register (pmpcfgx)
  • PMP Address Register (pmpaddrx)
  • Machine Security Configuration (mseccfg/mseccfgh)
  • Trigger Select Register (tselect)
  • Trigger Data Register 1 (tdata1)
  • Trigger Data Register 2 (tdata2)
  • Trigger Data Register 3 (tdata3)
  • Machine Context Register (mcontext)
  • Supervisor Context Register (scontext)
  • Debug Control and Status Register (dcsr)
  • Debug PC Register (dpc)
  • Debug Scratch Register 0 (dscratch0)
  • Debug Scratch Register 1 (dscratch1)
  • CPU Control and Status Register (cpuctrlsts)
  • Security Feature Seed Register (secureseed)
  • Time Registers (time(h))
  • Machine Vendor ID (mvendorid)
  • Machine Architecture ID (marchid)
  • Machine Implementation ID (mimpid)
  • Hardware Thread ID (mhartid)
• Performance Counters
  • Event Selector
  • Controlling the counters from software
  • Parametrization at synthesis time
  • FPGA Targets
• Exceptions and Interrupts
  • Privilege Modes
  • Interrupts
  • Internal Interrupts
  • Recoverable Non-Maskable Interrupt
  • Exceptions
  • Nested Interrupt/Exception Handling
  • Double Fault Detection
• Physical Memory Protection (PMP)
  • PMP Integration
  • PMP Granularity
  • PMP Enhancements
  • Custom Reset Values
• Security Features
  • Outputs
  • Data Independent Timing
  • Dummy Instruction Insertion
  • Bus integrity checking
  • Register file ECC
  • Register file write enable glitch detection
  • Register file read addresses glitch detection
  • ICache ECC
  • Hardened PC
  • Shadow CSRs
  • Dual core lockstep
• Debug Support
  • Interface
  • Parameters
  • Core Debug Registers
• Tracer
  • Output file
  • Disabling the tracer
  • Trace output format
• Verification
  • Ibex Core
  • Instruction Cache
• Verification Stages
  • V1 Checklist
  • V2 Checklist
  • V2S Checklist
  • Ibex SEC_CM Test Mapping
  • V3 Checklist
• Co-simulation System
  • Overview
  • Setup and Usage
  • Co-simulation details
• Test Plan
  • Goals
  • Testbench Architecture
  • Stimulus Strategy
  • Tests
• Coverage Plan
  • Introduction
  • Coverage Implementation
  • Microarchitectural Events and Behaviour
  • Cross Coverage
• RISC-V Formal Interface
  • Formal Verification
• History
  • References