System and Tool Requirements

The Ibex CPU core is written in SystemVerilog. We try to achieve a balance between the used language features (as described in our style guide) and reasonably wide tool support.

The following tools are known to work with the RTL code of Ibex. Please file an issue if you experience problems with any of the listed tools, or if you have successfully used a tool with Ibex which is not listed here.

  • Synopsys Design Compiler

  • Cadence Genus

  • Xilinx Vivado, version 2020.2 and up.

  • Verilator, version 4.104 and up.

  • Synopsys VCS, version at least 2020.03-SP2.

  • Cadence Incisive/Xcelium

  • Mentor Questa

  • Aldec Riviera Pro

To run the UVM testbench a RTL simulator which supports SystemVerilog and UVM 1.2 is required. The documentation of riscv-dv contains a list of supported simulators.

To compile code that runs on Ibex, you’ll need a RISC-V toolchain. This isn’t part of the core as such, but is necessary for verification. See the Verification section of the Reference Guide for more details about which toolchains the project currently uses for testing.

Tools with known issues

Not all EDA tools have enough SystemVerilog support to be able to work with the Ibex code base. Users of such tools are encouraged to file issues with the vendor. As a workaround, tools like sv2v can pre-process the source code to an older version of Verilog.

  • Intel (Altera) Quartus Prime Lite and Standard are not supported due to insufficient SystemVerilog support (issue #117).

  • Yosys cannot be used directly due to insufficient SystemVerilog support (issue #60). The syn folder in the Ibex repository contains scripts to use sv2v together with Yosys.

  • Icarus Verilog is not supported due to insufficient SystemVerilog support.