Standards Compliance
Ibex is a standards-compliant 32 bit RISC-V processor. It follows these specifications:
RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20211203 (December 4, 2021). Ibex implements the Machine ISA version 1.12.
RISC-V Bit-Manipulation Extension, version 1.0.0 and version 0.93 (draft from January 10, 2021)
PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) version 1.0
Many features in the RISC-V specification are optional, and Ibex can be parametrized to enable or disable some of them.
Ibex can be parametrized to support either of the following two instruction sets.
The RV32I Base Integer Instruction Set, version 2.1
The RV32E Base Integer Instruction Set, version 1.9 (draft from June 8, 2019)
In addition, the following instruction set extensions are available.
Extension |
Version |
Configurability |
---|---|---|
C: Standard Extension for Compressed Instructions |
2.0 |
always enabled |
M: Standard Extension for Integer Multiplication and Division |
2.0 |
optional |
B: Standard Extension for Bit-Manipulation Instructions |
1.0.0 + 0.93 [1] |
optional |
Zicsr: Control and Status Register Instructions |
2.0 |
always enabled |
Zifencei: Instruction-Fetch Fence |
2.0 |
always enabled |
Smepmp - PMP Enhancements for memory access and execution prevention on Machine mode |
1.0 |
always enabled in configurations with PMP see PMP Enhancements |
Ibex currently supports the following features according to the RISC-V Privileged Specification, version 1.12.
M-Mode and U-Mode
All CSRs listed in Control and Status Registers
Performance counters as described in Performance Counters
Vectorized trap handling as described at Exceptions and Interrupts
Footnotes