Standards Compliance

Ibex is a standards-compliant 32 bit RISC-V processor. It follows these specifications:

Many features in the RISC-V specification are optional, and Ibex can be parametrized to enable or disable some of them.

Ibex can be parametrized to support either of the following two instruction sets.

  • The RV32I Base Integer Instruction Set, version 2.1

  • The RV32E Base Integer Instruction Set, version 1.9 (draft from June 8, 2019)

In addition, the following instruction set extensions are available.

Table 1 Ibex Instruction Set Extensions




C: Standard Extension for Compressed Instructions


always enabled

M: Standard Extension for Integer Multiplication and Division



B: Draft Extension for Bit Manipulation Instructions

0.92 1


Zicsr: Control and Status Register Instructions


always enabled

Zifencei: Instruction-Fetch Fence


always enabled

Most content of the RISC-V privileged specification is optional. Ibex currently supports the following features according to the RISC-V Privileged Specification, version 1.11.

See PMP Enhancements for more information on Ibex’s experimental and optional support for the PMP Enhancement proposal from the Trusted Execution Environment (TEE) working group.



Note that while Ibex fully implements draft version 0.92 of the RISC-V Bit Manipulation Extension, this extension may change before being ratified as a standard by the RISC-V Foundation. Ibex will be updated to match future versions of the specification. Prior to ratification this may involve backwards incompatible changes. Additionally, neither GCC or Clang have committed to maintaining support upstream for unratified versions of the specification.